Re: Regression from 2.6.26: Hibernation (possibly suspend) broken on Toshiba R500 (bisected)

[Jesse Barnes]

On Thursday, December 4, 2008 7:25 pm Linus Torvalds wrote:
> On Thu, 4 Dec 2008, Linus Torvalds wrote:
> > Ok, the ICH6 LPC side has something similar, but not the same. Just two
> > ranges, and slightly less flexible wrt sizing.
> >
> > And ICH8/9/10 seems to have the same thing as ICH7.
>
> Here's a patch that implements what I think is the correct quirks (apart
> from the commented ICH6 lazy detail I didn't do).
>
> It would be very interesting to see if people affected get any printouts
> about IO decodes that don't show up in /proc/ioports...
>
> And I know I've looked for these kinds of things before in the Intel ICH
> docs, and apparently always missed these things (or been too lazy to
> react), so can somebody else see if they can find any other ranges like
> this? Maybe in non-LPC controllers?
>
> Jesse, are there any Intel chipset people who could once and for all say
> "these are the things we decode in our chipset" for _all_ chipsets and
> _all_ dynamic ranges? I've asked for that before. There must be people who
> know this, without having to wade through many thousands of pages of
> boring datasheets?

Yeah, I can get that info.  Sorry I haven't spent more time on this bug so 
far, I've been on vacation this week and very selective about which mails I 
reply to. :)

> The ICH datasheets tend to be 850 pages each, and there is more than one
> of them. And they _do_ differ in the details, even if there is a lot of
> sharing going on. So reading the docs is a huge effort, when there's bound
> to be somebody who just knows the answer.
>
> NOTE! This patch will just add a _printout_ of the IO regions it finds. It
> won't actually register them as known resources. So it won't make the
> kernel know to avoid them if they were to clash!
>
> Also, see the "This is not correct" for the ICH6 dynamically sized case.

Some of these may be listed as ACPI PNP ranges too...

Jesse
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