Re: [PATCH] x86: fix broken flushing in GART nofullflush path

[Ingo Molnar]

* Joerg Roedel <joerg.roedel@xxxxxxx> wrote:

> In the non-default nofullflush case the GART is only flushed when
> next_bit wraps around. But it can happen that an unmap operation unmaps
> memory which is behind the current next_bit location. If these addresses
> are reused it may result in stale GART IO/TLB entries. Fix this by
> setting the GART next_bit always behind an unmapped location.
> 
> Signed-off-by: Joerg Roedel <joerg.roedel@xxxxxxx>
> ---
>  arch/x86/kernel/pci-gart_64.c |    2 ++
>  1 files changed, 2 insertions(+), 0 deletions(-)

applied to tip/x86/iommu, thanks Joerg!

a stale iotlb should not cause any problems in this particular GART case, 
right? It might be a security leak in a security-domain enforcing iotlb 
case, but the GART is a DMA bouncing helper in essence. Can you see any 
failure mode of this bug?

	Ingo
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