[patch 0/9] x86, xsave: xsave/xrstor support

[Suresh Siddha]

This patchset adds the support for xsave/xrstor infrastructure for x86.
xsave/xrstor manages the existing and future processor extended states in x86
architecutre.

More info on xsave/xrstor can be found in the Intel SDM's located at
http://www.intel.com/products/processor/manuals/index.htm

The layout of the xsave/xrstor area extends from the 512-byte FXSAVE/FXRSTOR
layout.  xsave/xrstor area layout consists of:

     - fxsave/fxrstor area (512 bytes)
     - xsave header area (64 bytes)
     - set of save areas, each corresponding to a processor extended state

The number of save areas, the offset and the size of each save area is
enumerated by CPUID leaf function 0xd. 

This patch includes the basic xsave/xrstor infrastructure(supporting FP/SSE),
which includes:
      - context switch support,  extending traditional lazy restore mechanism
      - signal handling support, extending(using the software reserved bytes
	464..511 in the current 512byte layout of fxsave frame) the memory
	layout pointed out by the fpstate pointer in the sigcontext

More details in the patches to follow.

Signed-off-by: Suresh Siddha <suresh.b.siddha@xxxxxxxxx>
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