* Alan Cox <alan@xxxxxxxxxxxxxxxxxxx> wrote:
i dont get your last point. Firstly, we do an "outb $0x80" not an inb.outb not inb sorry yes
Secondly, outb $0x80 has no PCI posting side-effects AFAICS. Thirdly,It does. The last mmio write cycle to the bridge gets pushed out before the 0x80 cycle goes to the PCI bridge, times out and goes to the LPC bus.
ok. Is it more of a "gets flushed due to timing out", or a specified-for-sure POST flushing property of all out 0x80 cycles going to the PCI bridge? I thought PCI posting policy is up to the CPU, it can delay PCI space writes arbitrarily (within reasonable timeouts) as long as no read is done from the _same_ IO space address. Note that the port 0x80 cycle is neither a read, nor for the same address.