Re: SCSI breakage on non-cache coherent architectures

[Roland Dreier]

 > I've been debugging various issues on the PowerPC 44x embedded
 > architecture which happens to have non-coherent PCI DMA.
 > 
 > One of the problem I'm hitting is that one really need to enforce
 > kmalloc alignement to cache lines or bad things will happen (among
 > others with USB), for some reasons, powerpc failed to do so, I fixed it.

Heh... I hit the same problem literally 5 years ago:
    http://lwn.net/Articles/1783/

I implemented the __dma_buffer annotation:
    http://lwn.net/Articles/2269/

But DaveM said we should just use the PCI pool code instead:
    http://lwn.net/Articles/2270/

 - R.
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