Re: drm + 4GB RAM + swiotlb = drm craps out

[Dave Airlie]

> >
> > So when swiotlb happens, as you can guess it all falls apart as the
> > drm never calls sync functions at any stage...
>
> You would have hit this on any platform that does caching
> in the PCI controller as well.

We must not have a great intersect of radeon and such systems..

> Coherent memory was created for precisely the case where the cpu
> and the device frequently access the memory.
>
> 8MB is indeed a lot for the kind of allocation that the coherent
> DMA implementation uses.
>
> Does it really have to be all in one big 8MB chunk?  I doubt it.
> Perhaps you can therefore create multiple DMA pools instead?  See
> include/linux/dmapool.h

It currently is required to be in a big 8MB chunk as it gets chopped
up by the X server not the kernel, so kernel needs to allocate pages
to back it when X inits, yes this is ugly, no it can't be fixed
without time-travelling and fixing deployed X servers...

Really we probably only need the ring buffer to be in coherent memory,
the rest of the stuff is used for DMA buffers which are mainly filled
by the CPU and read by the GPU. However I cannot change this without
breaking X, the solution is really to use TTM for this sort of
stuff.... I'm a bit worried as the AGP driver now uses vmalloc_32
which really is a meaningless interface on 64-bit systems..

Dave.
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