Re: Which CPU for VIA C7/Esther?

[Dave Jones]

On Mon, Feb 12, 2007 at 11:46:46PM +0000, Simon Arlott wrote:

 > MVIAC3_2 doesn't enable X86_GOOD_APIC

which is pretty irrelevant unless you have a dual C7.

 > , try M686 (Pentium-Pro) - but that won't enable MMX and SSE (via -march=c3-2).

If gcc generated SSE/MMX instructions that would be a bug. (hint: it doesn't).

 > These CPUs support SSE2 too... 

The SSE/SSE2/SSE3 etc support for userspace is unconditional. The context switch paths will
save/restore the registers regardless of the CPU you've compiled your kernel for.
The only SSE code in the kernel is the memcpy code (which wasn't that big a win when
I last tried it on VIA due to their poor memory bandwidth), and the RAID code, which
gets tested at runtime rather than compile time.

 > Also, for the C7 you'll want CRYPTO_DEV_PADLOCK_* (Hardware Crypto Devices, Support for VIA PadLock ACE) and HW_RANDOM_VIA (VIA HW Random Number Generator support).

Yes. But these aren't dependant on any CPU config options.

		Dave

-- 
http://www.codemonkey.org.uk
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