Re: The change "PCI: assign ioapic resource at hotplug" breaks my system

[Roland Dreier]

One piece of information that might be useful is that lspci shows a
difference in the configuration of the PCI bridge IOAPIC.  In the good
(working) case, the IOAPIC memory region 0 is disabled, while in the
bad case it is enabled.

Here are full details: first, the good/working case:

	04:01.1 PIC: Advanced Micro Devices [AMD] AMD-8132 PCI-X IOAPIC (rev 12) (prog-if 10 [IO-APIC])
		Subsystem: Advanced Micro Devices [AMD] AMD-8132 PCI-X IOAPIC
		Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
		Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
		Latency: 0
		Region 0: Memory at <ignored> (64-bit, non-prefetchable)
	00: 22 10 59 74 06 00 00 02 12 10 00 08 00 00 00 00
	10: 04 e0 af fe 00 00 00 00 00 00 00 00 00 00 00 00
	20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 59 74
	30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00
	40: 00 00 00 00 03 00 00 00 04 e0 af fe 00 00 00 00

Then the bad (non-working e1000) case:

	04:01.1 PIC: Advanced Micro Devices [AMD] AMD-8132 PCI-X IOAPIC (rev 12) (prog-if 10 [IO-APIC])
		Subsystem: Advanced Micro Devices [AMD] AMD-8132 PCI-X IOAPIC
		Control: I/O- Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B-
		Status: Cap- 66MHz- UDF- FastB2B- ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR-
		Latency: 0
		Region 0: Memory at e2100000 (64-bit, non-prefetchable) [size=4K]
	00: 22 10 59 74 06 00 00 02 12 10 00 08 00 00 00 00
	10: 04 00 10 e2 00 00 00 00 00 00 00 00 00 00 00 00
	20: 00 00 00 00 00 00 00 00 00 00 00 00 22 10 59 74
	30: 00 00 00 00 50 00 00 00 00 00 00 00 00 00 00 00
	40: 00 00 00 00 03 00 00 00 04 00 10 e2 00 00 00 00

I have no idea whether there's any significance to this.

 - R.
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