Re: question regarding cacheline size
From: Jeff Garzik
Date: Thu Sep 07 2006 - 11:58:40 EST
Tejun Heo wrote:
arch/i386/pci/common.c overrides cacheline size to min 32 regardless of
actual size. So, we seem to be using larger cacheline size for MWI
already.
It clamps the minimum size to 32, yes, but on modern machines common.c
configures it to a larger size.
Jeff pointed out that there actually are devices which limit CLS config.
IMHO, making PCI configure CLS automatically and provide helpers to LLD
to override it if necessary should cut it.
We still have to add a raft of quirks, if we start automatically
configurating CLS... Also, many PCI devices hardcode it to zero.
If we start configuring CLS automatically, I forsee a period of breakage...
Jeff
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