Re: question regarding cacheline size

[Tejun Heo]

Matthew Wilcox wrote:
> On Thu, Sep 07, 2006 at 02:33:25PM +0200, Arjan van de Ven wrote:
> > > So I think we should redo the PCI subsystem to set cacheline size during
> > > the buswalk rather than waiting for drivers to ask for it to be set.
> > ... while allowing for quirks for devices that go puke when this
> > register gets written ;)
> >
> > (afaik there are a few)
>
> So you want:
>
> 	unsigned int no_cls:1;	/* Device pukes on write to Cacheline Size */
>
> in struct pci_dev?

The spec says that devices can put additional restriction on supported 
cacheline size (IIRC, the example was something like power of two >= or 
<= certain size) and should ignore (treat as zero) if unsupported value 
is written.  So, there might be need for more low level driver 
involvement which knows device restrictions, but I don't know whether 
such devices exist.

--
tejun
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