On Tue, 8 Aug 2006, Alan Shieh wrote:
With help from the Etherboot Project, I've recently implemented such a driver for Etherboot 5.4. It currently supports PIO NICs (e.g. cards that use in*/out* to interface with CPU). It's currently available in a branch, and will be merged into the trunk by the Etherboot project. It works reliably with QEMU + PXELINUX, with the virtual ne2k-pci NIC.
Barring unforseen issues, I should get MMIO to work soon; target platform would be pcnet32 or e1000 on VMware, booted with PXELINUX.
Addressing a very narrow terminology issue:
I think that there a misuse of terms here. PIO, or Programmed I/O, is data transfer mode where the CPU explicitly passes data to and from a device through a single register location.
The term is unrelated to the device being addressed in I/O or memory space. On the x86, hardware devices were usually in the I/O address space and there are special "string" I/O instructions, so PIO and I/O space were usually paired. But processors without I/O instructions could still do PIO transfers.
Memory Mapped I/O, MMIO, is putting the device registers in memory space. In the past it specifically meant sharing memory on the device e.g. when the packet buffer memory on a WD8013 NIC was jumpered into the ISA address space below 1MB. The CPU still controls the data transfer, generating a write for each word transfered. But the address changed with each write, just like a memcpy.
Today "MMIO" is sometimes misused to mean simply using a PCI memory mapping rather than a PCI I/O space mapping. PCI actually has three address spaces: memory, I/O and config spaces. Many devices allow accessing the operational registers either through I/O or memory spaces.