Dual core Athlons and unsynced TSCs

[Lee Revell]

It's been known for quite some time that the TSCs are not synced between
cores on Athlon X2 machines and this screws up the kernel's timekeeping,
as it still uses the TSC as the default time source on these machines.

This problem still seems to be present in the latest kernels.  What is
the plan to fix it?  Is the fix simply to make the kernel use the ACPI
PM timer by default on Athlon X2?

Lee

-
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/