Re: keylargo PCI USB controller nor enabled on G4 xserve

[Benjamin Herrenschmidt]

Can you try that workaround (quite ugly until I figure out what's
really going on in there) and let me know if it makes any difference ?

===== arch/ppc/kernel/pci.c 1.43 vs edited =====
--- 1.43/arch/ppc/kernel/pci.c	2004-08-26 16:43:07 +10:00
+++ edited/arch/ppc/kernel/pci.c	2004-09-17 11:19:10 +10:00
@@ -33,6 +33,7 @@
 unsigned long isa_io_base     = 0;
 unsigned long isa_mem_base    = 0;
 unsigned long pci_dram_offset = 0;
+int pcibios_assign_bus_offset = 1;
 
 void pcibios_make_OF_bus_map(void);
 
@@ -1263,7 +1264,7 @@
 		bus = pci_scan_bus(hose->first_busno, hose->ops, hose);
 		hose->last_busno = bus->subordinate;
 		if (pci_assign_all_busses || next_busno <= hose->last_busno)
-			next_busno = hose->last_busno+1;
+			next_busno = hose->last_busno + pcibios_assign_bus_offset;
 	}
 	pci_bus_count = next_busno;
 
===== arch/ppc/platforms/pmac_pci.c 1.22 vs edited =====
--- 1.22/arch/ppc/platforms/pmac_pci.c	2004-08-04 21:55:48 +10:00
+++ edited/arch/ppc/platforms/pmac_pci.c	2004-09-17 11:18:41 +10:00
@@ -50,6 +50,7 @@
 #endif /* CONFIG_POWER4 */
 
 extern u8 pci_cache_line_size;
+extern int pcibios_assign_bus_offset;
 
 struct pci_dev *k2_skiplist[2];
 
@@ -565,6 +566,14 @@
 
 	init_p2pbridge();
 	fixup_nec_usb2();
+	
+	/* We are still having some issues with the Xserve G4, enabling
+	 * some offset between bus number and domains for now when we
+	 * assign all busses should help for now
+	 */
+	if (pci_assign_all_busses)
+		pcibios_assign_bus_offset = 0x10;
+
 #ifdef CONFIG_POWER4 
 	/* There is something wrong with DMA on U3/HT. I haven't figured out
 	 * the details yet, but if I set the cache line size to 128 bytes like


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