NUMA for abstract bus-masters (was Re: sched_domains + NUMA issue)

[Guennadi Liakhovetski]

Hi

I recently raised a discussion on the ARM-kernel ml, so, I just want to 
check if it would raise any interest here.

I was thinking about architectures, where multiple memory (RAM) pools 
exist on different buses, and various bus-masters on the system have 
different distances to various RAMs. Say, distance can be defined as the 
number of bridges to cross, if that RAM is at all accessible, or infinity 
otherwise.

The API would on one hand allow to register such RAM pools at different 
locations, and on the other hand, requests for RAM with a device pointer 
([dma|pci]_alloc_*) would try to find the nearest RAM available.

And one would have to optimise those allocated buffers for n (typically 2) 
bus-masters (e.g., CPU and a device) with various weights...

And the idea would be to re-use (some of) the NUMA framework.

This would be another approach to tackle problems, addressed by the James' 
dma_declare_coherent_memory patch.

So, does this at all sound reasonable? Anybody finds it useful?

Thanks
Guennadi
---
Guennadi Liakhovetski

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