Re: page align emergency stack

From: David Gibson
Date: Mon Jul 19 2004 - 01:04:52 EST

On Fri, Jul 16, 2004 at 11:39:01AM +1000, David Gibson wrote:
> On Fri, Jul 16, 2004 at 11:11:41AM +1000, Anton Blanchard wrote:
> >
> >
> > > Do we actually need to do this? I noted that the old guard pages were
> > > page aligned, but couldn't see any particular reason for it, so I
> > > didn't transfer the alignment to the new version.
> >
> > The ABI requires us to have 128 bit alignment doesnt it? Im thinking
> > about what would happen if we saved altivec registers to the stack.
> Ok, that's not quite the same thing as page alignment...

Ok, here's a patch that just applies the weaker 128-byte alignment

Andrew, please apply

The PPC64 ABI requires the stack to be 128 byte aligned (and that can
become important if AltiVec registers are saved there). In the
kernel, that's usually dealt with by the fact that the stack has a
page more-or-less to itself. However, the emergency stacks (used in
SMP bringup and when we detect a bad stack pointer) aren't necessarily
page aligned, or anything aligned for that matter. This patch applies
the necessary alignement constraint to them.

Signed-off-by: David Gibson <dwg@xxxxxxxxxx>

Index: working-2.6/arch/ppc64/kernel/pacaData.c
--- working-2.6.orig/arch/ppc64/kernel/pacaData.c
+++ working-2.6/arch/ppc64/kernel/pacaData.c
@@ -29,8 +29,10 @@

/* Stack space used when we detect a bad kernel stack pointer, and
* early in SMP boots before relocation is enabled.
+ *
+ * ABI requires stack to be 128-byte aligned
-char emergency_stack[PAGE_SIZE * NR_CPUS];
+char emergency_stack[PAGE_SIZE * NR_CPUS] __attribute__((aligned(128)));

/* The Paca is an array with one entry per processor. Each contains an
* ItLpPaca, which contains the information shared between the

David Gibson | For every complex problem there is a
david AT | solution which is simple, neat and
| wrong.
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