Re: 2.6.1 and irq balancing

[Ed Tomlinson]

Hi,

What is the load on the box when this is happening?  If its low think
this is optimal (for cache reasons).

Ed Tomlinson

On January 10, 2004 06:14 pm, Ethan Weinstein wrote:
> Greetings all,
> 
> I upgraded my server to 2.6.1, and I'm finding I'm saddled with only 
> interrupting on CPU0 again. 2.6.0 does this as well. This is the 
> Supermicro X5DPL-iGM-O (E7501 chipset), 2 Xeons@xxxxxx HT enabled. 
> /proc/cpuinfo is normal as per HT, displaying 4 cpus.
> 2.4.2(3|4) exhibited this behaviour as well, until I applied patches 
> from here: 
> http://www.hardrock.org/kernel/2.4.23/irqbalance-2.4.23-jb.patch, et al.
> 
> 
>             CPU0       CPU1       CPU2       CPU3
>    0:    1572323          0          0          0    IO-APIC-edge  timer
>    2:          0          0          0          0          XT-PIC  cascade
>    3:      23520          0          0          0    IO-APIC-edge  serial
>    8:          2          0          0          0    IO-APIC-edge  rtc
>    9:          0          0          0          0   IO-APIC-level  acpi
>   14:         10          0          0          0    IO-APIC-edge  ide0
>   16:         30          0          0          0   IO-APIC-level 
> sym53c8xx
 22:       4162          0          0          0   IO-APIC-level 
> eth0 48:       7798          0          0          0   IO-APIC-level 
> aic79xx 49:       3385          0          0          0   IO-APIC-level 
> aic79xx 54:      17062          0          0          0   IO-APIC-level 
> eth1 NMI:          0          0          0          0
> LOC:    1572002    1572251    1572250    1572243
> ERR:          0
> MIS:          0
> 
> 
> THey keyboard isn't working either, but we see the i8042..
> 
> serio: i8042 KBD port at 0x60,0x64 irq 1
> 
> 
> -Ethan
> -
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