Re: [RFC] Relaxed PIO read vs. DMA write ordering

[Grant Grundler]

On Thu, Jan 08, 2004 at 09:36:55AM -0800, Jesse Barnes wrote:
> > BTW, Jesse, did you look at part II of Documentation/DMA-ABI.txt?
> 
> I remember seeing discussion of the new API, but haven't read that doc
> yet.  Since most drivers still use the pci_* API, we'd have to add a
> call there, but we may as well make the two APIs as similar as possible
> right?

That would be my preference too.

I haven't studied "part II" closely enough to figure out if adding
pci_sync_consistent() would outright replace much of the DMA-API
interface. The main issue is cacheline ownership.

pci_sync_consistent() needs to indicate CPU wants ownership of outstanding
cachelines vs IO device wanting to own them.
SN2 doesn't care about the latter case since it's "mostly coherent".
SN2 just needs to flush in-flight DMA and it's coherent again.
But older non-coherent platforms do care.

I trust James understands this better than I given the fun
he's had with old parisc HW (715/50).

grant
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