Re: [RFC] Relaxed PIO read vs. DMA write ordering

[Christoph Hellwig]

On Thu, Jan 08, 2004 at 08:23:49AM -0800, Leonid Grossman wrote:
> Yes, this is exactly how (at least our 10GbE) PCI-X ASICs work.
> If the RO bit is set, the device decides whether the transaction
> requires strong ordering,
> and sets RO attribute accordingly.

Do you have a pointer to the driver source?  This would probably
make a good reference driver for Jesse's suggestion.

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