Re: PCI Express support for 2.4 kernel

[Vladimir Kondratiev]

Gabriel Paubert wrote:

Gabriel,
I verified with PCI-E designers,
uncacheable memory relates to snoop/non-snoop, not to buffering in 
bridge. Bridge will still buffer writes.
The only way to be sure data has arrived, is to perform read.

Vladimir.

> > > Further, PCI posting:  a writeb() / writew() / writel() will not be 
> > > flushed immediately to the processor.  The CPU and/or PCI bridge may 
> > > post (delay/combine) such writes.  I do not think this is a desireable 
> > > effect, for PCI config register accesses.
> > >
> > >      
> > Good point. Fixed.
> >    
>
> Here I'm somehwat lost. Writes to uncacheable RAM will be in program 
> order and never combined. The bridge itself should not post writes to 
> config space. So it's a matter of pushing the write to the processor
> bus, a PCI read looks very heavy for this. Isn't there a more
> lightweight solution ?
>
> 	Regards,
> 	Gabriel
>
>  

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