Re: SMP broken on Dell PowerEdge 4100/200 under 2.6.0-testxx?

[Zwane Mwaikambo]

On Mon, 8 Dec 2003, bill davidsen wrote:

> I think the most confusing thing about this was the choice of
> "noirqbalance" as an option to mean "do balance irqs." I'm not sure that
> the default to put all irqs on a single CPU is optimal in any case, but
> the naming is particularly bad.

Actually, noirqbalance means no in kernel irq balancer. ia32 SMP systems
before P4 tend to RR interrupt handling via hardware by utilising an APIC
bus arbitration scheme. P4 doesn't, one reason being the missing
Arbitration ID register and the usage of a bus cycle to determine which
processor should handle the interrupt depending on the status of the Task
Priority Register on each local apic (processor). So in essence we should
be using the TPR to do interrupt balancing decisions with P4/Xeon. So all
noirqbalance will do is disable in kernel balancer.
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