RE: [PATCH] 2.6 workaround for Athlon/Opteron prefetch errata

[richard . brunner]

Potentially, any address can be a candidate. If you assume a sequential
access pattern for data, addresses toward the back of the cache-line
(but not the last few bytes) are less likely to hit the errata
because hopefully the page that the cacheline is in is 
already "faulted in". But that is no guarantee.


] -Rich ...
] AMD Fellow
] richard.brunner at amd com 

> -----Original Message-----
> From: Jamie Lokier [mailto:jamie@xxxxxxxxxxxxx] 
> Sent: Thursday, September 11, 2003 9:59 AM
> To: Andi Kleen
> Cc: Brunner, Richard; linux-kernel@xxxxxxxxxxxxxxx; 
> akpm@xxxxxxxx; torvalds@xxxxxxxx
> Subject: Re: [PATCH] 2.6 workaround for Athlon/Opteron prefetch errata
> 
> 
> Andi Kleen wrote:
> > +static int is_prefetch(struct pt_regs *regs, unsigned long addr)
> 
> Do I understand that certain values of "addr" can't be due to the
> erratum?
> 
> In which case, could you skip most of the is_prefetch() instruction
> decoder with a test like this?:
> 
> 	if ((addr & 3) == 0)
> 		return 0;
> 
> I'm not sure from the description of the erratum what, exactly, are
> the possible addresses which can appear in the fault information.
> 
> -- Jamie
> 

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