Re: Virtual alias cache coherency results (was: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this)

[Jamie Lokier]

Russell King wrote:
> Maybe those StrongARM chips don't exhibit the write buffer bug?  Remember,
> I said _SOME_ StrongARM-110 chips exhibit the problem.  I did not say
> _ALL_ StrongARM-110 chips exhibit the problem.

I never assumed they all have the bug.  Credit me with at least
reading what you wrote before! :)

The results indicate some StrongARM-110 systems which _don't_ exhibit
the write buffer bug _do_ exhibit some _other_ cause of non-coherence.

> > It means that your VIVT explanation and workaround does not explain
> > those results, so I cannot have confidence that your workaround fixes
> > those particular ARM devices.
> 
> Well, as far as I'm concerned, I completely believe that I have explained
> it entirely, and I still don't know why you're trying to make this more
> difficult than it factually is.

I'm thinking the same of you! :)

All I asked is whether _all_ ARMs appear coherent to userspace now, and
you replied with:

> It's relatively simple, and I'm not sure why its causing such
> misunderstanding.  Let me try one more time:

and proceeding to answer a different question to the one I asked.

So, neither of us knows if all ARMs appear coherent to userspace, with
the latest kernel, ...

> Well, once you collect the kernel information and forward it to me, I
> can have a look.

...until we learn what kernel versions the Netwinder folks are
running, or they kindly run the test on a new kernel.

Thanks,
-- Jamie
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