Re: Virtual alias cache coherency results (was: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this)

[Richard Curnow]

Hi Jamie,

Thanks for posting the summary of your experiment - very useful!

* Jamie Lokier <jamie@xxxxxxxxxxxxx> [2003-09-10]:
> 
> Validity of SHMLBA value
> ........................
> 
> Many CPUs offer virtual cache coherency when the aliases are separated
> by a certain CPU-dependent multiple.  In principle, all
> Linux-supported architectures _should_ have a multiple which makes
> virtual aliases coherent, because it's defined in the API as "SHMLBA".
> However, on some specific CPUs, no coherent multiple was found.
> 
>     Valid kernel SHMLBA:	Sparc, PA-RISC, MIPS
> 				(plus all the coherent architectures)
>     SHMLBA not valid:		ARM, m68k
>     SHMLBA not defined:		SH

What's the basis for deciding wheter SHMLBA is defined or not? There are
definitions of SHMLBA in include/asm-sh/shmparam.h and
include/asm-sh64/shmparam.h for the kernel.  The sh64 /usr/include/asm
headers have effectively the same thing (not identical because the copy
I'm looking at hasn't been synced with the latest kernel sources), and I
assume the sh userland is OK too (haven't checked though).

In both cases the kernel headers are showing correct and useful values :
16k for SH-4 in the sh file (16k direct-mapped, or 32k 2-way associative
on latest devices), 8k for SH-5 in the sh64 file (32k 4-way
associative).

Cheers
Richard

-- 
Richard \\\ SuperH Core+Debug Architect /// .. At home ..
  P.    /// richard.curnow@xxxxxxxxxx  ///  rc@xxxxxxxxxx
Curnow  \\\ http://www.superh.com/    ///  www.rc0.org.uk
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