Re: [2.4 patch] fix CONFIG_X86_L1_CACHE_SHIFT

[Jamie Lokier]

Adrian Bunk wrote:
> > Why requires? On x86, the cpu caches are fully coherent. A too small L1 
> > cache shift results in false sharing on SMP, but it shouldn't cause the 
> > described problems.
> >...
> 
> Thanks for the correction, I falsely thought CONFIG_X86_L1_CACHE_SHIFT 
> does something different than it does.

Were there any changes in the kernel to do with PCI MWI settings?

(MWI == memory write and invalidate)

If MWI is set incorrectly, I think PCI DMA is capable of breaking x86
cache coherence.

-- Jamie

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