Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this

[Davide Libenzi]

On Wed, 3 Sep 2003, Nagendra Singh Tomar wrote:

> Jamie,
> 	Just wondered if the store buffer is snooped in some
> architectures. In that case I believe the OS need not do anything for
> serialization (except for aliases, if they do not hit the same cache line).
> In x86 store buffer is not snooped which leads to all these serialization
> issues (other CPUs looking at stale value of data which is in the store
> buffer of some other CPU).
> Pl correct me if I have got anything wrong/

To avoid the so called 'load hazard' (that, BTW, triggers read over
writes, that are not allowed in x86) you have two options. Snoop the write
buffer or flush it upon L1 miss. Otherwise you might end up getting stale
data from L2.



- Davide

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