Re: x86, ARM, PARISC, PPC, MIPS and Sparc folks please run this

[Mike Fedyk]

On Fri, Aug 29, 2003 at 08:41:01AM -0700, Larry McVoy wrote:

> ====== sparc.bitmover.com ======
> Test separation: 8192 bytes: FAIL - cache not coherent

> VM page alias coherency test: minimum fast spacing: 16384 (2 pages)
> 0.29user 0.02system 0:00.31elapsed 99%CPU (0avgtext+0avgdata 0maxresident)k
> 0inputs+0outputs (107major+36minor)pagefaults 0swaps
> Linux sparc.bitmover.com 2.2.18 #2 Thu Dec 21 18:53:16 PST 2000 sparc64 unknown
> cpu		: TI UltraSparc IIi
> fpu		: UltraSparc IIi integrated FPU
> promlib		: Version 3 Revision 11
> prom		: 3.11.12
> type		: sun4u
> ncpus probed	: 1
> ncpus active	: 1
> BogoMips	: 539.03
> MMU Type	: Spitfire

Does this mean that userspace has to take into consideration that the isn't
coherent for adjacent small memory accesses on sparc?  What could happen if
it doesn't, or does it need to at all?
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