On Wed, Apr 16, 2003 at 04:55:32PM +0200, Matthew Wilcox wrote:
> On Wed, Apr 16, 2003 at 04:43:12PM +0200, Andi Kleen wrote:
> > On sparc64. But is that true too for all other 64bit architectures supported?
> >
> > e.g. How about PA-RISC? (always seems to do things differently)
>
> As you know our only two atomic ops are load-and-clear 32-bit quantity and
> load-and-clear 64-bit quantity. so we take one of the hashed spinlocks ..
Sure, but you use a 64bit read/store in set_bit/clear_bit etc., right?
If yes then you can't use this unless you rewrite them to use 32bit store
- otherwise it will conflict with the atomic_t counter in the 64bit slot
which is not protected.
I think my current patch is fine for you - you can still optimize it
this way, but it should already work. Jakub's version would break though.
-Andi
-
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