On Tue, Mar 25, 2003 at 12:33:10PM +0100, Ivan Kokshaysky wrote:
> > The x86-64 port extract it like this in setup.c:
> > if (c->x86_capability[0] & (1<<19))
> > c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
> > }.
> > I changed its pci code to use that directly now. i386 likely
> > should too. When no CLFLUSH is supported you can safely assume 32byte
> > cachelines.
>
> Apparently it's fine for K8, but what about Athlons? They have
> bit 19 == 0 and 64-byte cache lines.
Ok.
Athlon likely reports its cacheline size too in 8000_0005 / ECX (I think,
not checked), but it doesn't have the CLFLUSH bit, you're right.
> BTW, the "AMD Processor Recognition Application Note" calls bit 19
> "Multiprocessing Capable". ;-)
Hmm, yes it's broken. 19 is CFLUSH in the 8000_0001 extended CPUID word,
but not in index 0000_0001. Copied wrong from cpufeature.h.
Probably it should reinitialize x86_capability[0] from 80000001 when
available, but need to double check the list.
Broken in i386 too.
-Andi
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