> On Sat, 15 Feb 2003, Roger Luethi wrote:
> >
> > Thanks for raising that issue. It is my understanding that PIO ops are
> > synchronous (on IA-32). If that is correct, problems should only occur if
> > the driver is built with MMIO support, no?
>
> No, even PIO ops are asynchronous. They are _more_ synchronous than the
> MMIO ones (I think the CPU waits until they hit the bus, and most bridges
Hmmm... A recent thread on PCI write posting seemed to confirm my view [1].
What am I missing here?
------------------------------ cut here -----------------------------------
From: Alan Cox <alan@lxorguk.ukuu.org.uk>
Subject: Re: Linux 2.4.21-pre3-ac4
Date: 12 Jan 2003 20:40:54 +0000
On Sun, 2003-01-12 at 19:51, Benjamin Herrenschmidt wrote:
> What about PCI write posting ? How can we enforce the 400ns delay here ?
For i/o space it is ok as in*/out* are synchronous. For mmio right now I
don't know. I need to talk to Andre about that for SATA. I guess for the
PPC its going to be fun
[...]
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> don't need a IO read to force it out. But considering the wide variety of
> PCI bridges out there I bet there are some that will post even PIO writes
> and might hold on to them for some time, especially if other activity like
> DMA keeps the bus busy.
There was some talking about hwif->IOSYNC() (for IDE). That might be
interesting for other devices, too. It could resolve to a nop for
synchronous operations, and say a read* for MMIO. IMHO it shouldn't be up
to a driver maintainer to figure out what sync op some arch the driver may
run on needs. What a maintainer typically _can_ provide is type of
operation (MMIO/PIO) and a register that is considered safe for a sync
read.
Roger
[1] http://marc.theaimsgroup.com/?l=linux-kernel&m=104240180906935&w=4
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