On Tue, 2003-02-04 at 12:45, Herman Oosthuysen wrote:
> Hi there,
>
> From my experience, the speed issue is caused by misalligned memory
> accesses, causing inefficient SDRAM to Cache movement of data and
> instructions.
>
> I don't think that you necessarily need a modification to the compiler.
> What you can do is carefully place the ALLIGN switch in a few critical
> places in the kernel code, to ensure that the code and data will be
> properly alligned for whatever processor it is compiled for, be that a
> Pentium, an ARM, a MIPS or whatever.
>
I guess I would like the compiler to do that without having to go
in and futz the code.
> It would be nice if GCC can be suitably improved to do this correcly for
> all architectures, but a little bit of human help can do wonders,
> without having to fork the GCC project.
>
> Cheers,
-- Timothy D. Witham - Lab Director - wookie@osdlab.org Open Source Development Lab Inc - A non-profit corporation 15275 SW Koll Parkway - Suite H - Beaverton OR, 97006 (503)-626-2455 x11 (office) (503)-702-2871 (cell) (503)-626-2436 (fax)- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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