Benjamin Herrenschmidt wrote:
>On Mon, 2003-01-13 at 20:19, Ross Biro wrote:
>
>
>
>>and read the alt status register to get a delay.
>>
>>This is technically a spec violation, but it's probably safe. I'm going
>>to send an email to a couple of the drive manufacturers and see what
>>they think.
>>
>>
>
>Or get back to my original idea of an IOSYNC() callback in hwif. For
>standard PCI controllers with DMA, it's enough to read the dma_status
>register which is on the same bus path. Others will have to provide
>some implementation or be unsafe on some non-x86. What do you think ?
>
I think that's a very good idea provided that we know that the
dma_status register exists and is on the same bus path. That should be
true for all modern IDE controllers on the x86. But is not a completely
general solution.
One thing that we should keep in mind, is that the IDE controller could
buffer the write as well. I've seen some evidence that Promise chips
might attempt to buffer things like resets until a UDMA burst is
complete. I guess we have to assume that any controller that does such
a thing will also provide a way of knowing when the command has actually
been sent to the drive.
If anyone is curious, I believe I've got the hardware to see how long
after the PCI bus sees an i/o command that it makes it to the drive, but
this would only be trivia that applies to the motherboard we test it on
with the settings currently in place and should not be relied on.
Ross
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This archive was generated by hypermail 2b29 : Wed Jan 15 2003 - 22:00:47 EST