On Tuesday 07 January 2003 02:42 pm, Andrew Theurer wrote:
[ Snip! ]
>
> I am bringing this up, because I recall James Cleverdon having some code
> which allows interrupts to be dynamically routed to two CPU destinations, a
> pair of CPUs with consecutive CPU ID's. Interrupts are dynamically routed
> to the least loaded CPU, and if both are idle, to the CPU with the lower
> CPUID. I like this idea, because when in HT, if consecutive logical CPU
> ID's map to one physical core, we get to use "whole" processor, and both
> destinations share the cache. Anyway, just a thought.
>
> -Andrew Theurer
Here's a quick respin of my old TPR patch for 2.5.55.
--
James Cleverdon
IBM xSeries Linux Solutions
{jamesclv(Unix, preferred), cleverdj(Notes)} at us dot ibm dot com
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