Hello,
> There may be options in your BIOS to disable this "feature".
> Look for things like "PCI byte-merging" and/or "PCI read
> prefetch". I haven't had access to one of the new SIS based
> P4 systems yet, so I don't know how they are setup or exactly
> how they are violating the PCI spec. The test will fail
> either if byte-merging or read prefetch occurs and perhaps if
> there is an MTTR covering the memory mapped region of the
> chip that is set to write combining mode (I don't think that
> the mb() we issue after every memory write helps in this last case).
I've been looking at the PCI option in the BIOS...
1st part is mapping IRQ to PCI slots...
Then, you have :
PCI/VGA Palette Snoop Disabled
PCI Latency Timer 32
Primary VGA BIOS PCI VGA Card
USB Function Enabled
USB2.0 Function Enabled
Onboard LAN Boot ROM Disabled
Maybe related, the memory config :
SDRAM Configuration By SPD
Chipset clock mode Synchronous
SDRam Command Lead-off time Auto
Graphics Aperture Size 256 MB
AGP Capability 4x Mode
AGP Fast Write Capability Enabled
Video Memory Cache Mode UC
Memory hole at 15M-16M Disabled
PCI 2.1 Support Enabled
Onboard PCI IDE Enable Both
IDE Bus Master Support Enabled
Could it be PCI 2.1 Support ? Don't think because I've restarted
with it disabled, and I still have the same problem...
Regards,
Paul
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This archive was generated by hypermail 2b29 : Tue Jan 07 2003 - 22:00:29 EST