>> The main reason why the new driver "breaks" where the old one
>> doesn't is that the new driver does not perform an extra register
>> read to work-around chipsets that screw up memory mapped I/O. There
>> are four solutions to this problem:
>
> just to be sure...you're not talking about PCI posting right?
> can you explain in a bit more detail the exact behavior that is the
> problem ? (I'm sure a lot of other drivers will suffer the same so I
> consider it of general interest)
PCI posting is an expected (and desired) characteristic of PCI, so, no
I'm not complaining about that. According to the PCI spec, prefetch
is only allowed for devices that explicitly indicate that they support
it (via a bit in their BAR registers). Further, write combining and
byte merging are only allowed for prefetchable regions. The Adaptec
parts do not set the prefetch bit and do not support either of these
options (most registers are 8bits anyway, so there was nothing to
gain by complicating the part with this support). Some BIOSes ignore
this rule and attempt to prefetch and/or write combine transactions
to these chips. Other BIOSes actually have an option so that the user
can say "ignore the rules". The new tests are designed to weed out
this broken behavior and to fallback to PIO where prefetch and write
combining cannot come into play.
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This archive was generated by hypermail 2b29 : Tue Jan 07 2003 - 22:00:21 EST