> The reason this is a problem, is that when the LSI/StoragTEK
> controllers present their luns, AVT is enabled.
Others have answered the kernel questions, but just a note that you really
don't want to do load balancing in this environment.
the way AVT works is that a LUN is locked to a specific controller (although
it has a ghost on the alternate controller). If you send an I/O packet to the
alternate controller, the controllers will immediately negotiate to transfer
the LUN across (AVT is Auto Volume Transfer). It takes quite a while (in I/O
terms) for the LUN to transfer, so if you load balance to this array you'll
end up killing performance because most of the time will be spent oscillating
the LUN.
The way the setup was intended to work was for simple failover, where you only
use an alternate path if the primary fails.
In general, arrays that can gain performance from controller load balancing
tend to be extremely expensive (EMC being the one that springs immediately to
mind).
James
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