From: Linus Torvalds <torvalds@transmeta.com>
Date: Fri, 4 Oct 2002 18:02:15 -0700 (PDT)
On Fri, 4 Oct 2002, Alexander Viro wrote:
> Hell knows. The only explanation I see (and that's not worth much) is that
> we somehow confuse the chipset and get crapped on something like next cache
> miss.
I don't see any better explanation right now, so I guess we just revert
that thing.
The people seeing this don't happen to be on Serverworks chipsets
are they?
I've seen a bug on serverworks where back to back PCI config
space operations can cause some to be lost or corrupted.
Another theory is that some device just dislikes being given
a 0 in one of it's base registers, but somehow ~0 is ok :-)
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This archive was generated by hypermail 2b29 : Mon Oct 07 2002 - 22:00:49 EST