On Tue, Oct 01, 2002 at 09:42:02AM +0100, Russell King wrote:
>
> On Tue, Oct 01, 2002 at 03:34:17PM +1000, David Gibson wrote:
> > I don't see an easy one: PPC 4xx has non-coherent cache, so we have to
> > mark consistent memory non-cacheable. We want to make the normal
> > lowmem mapping use large page TLB entries, so we can't frob the
> > attribute bits on the pages in place. That means we need to create a
> > new, non-cacheable mapping for the physical RAM we allocate, which in
> > turn means allocating a chunk of kernel virtual memory.
>
> Same problem on ARM. I just haven't got the motivation to rewrite the
> bits of the kernel that need to be rewritten to make it work.
>
> Have you checked that your pte/pmd allocation functions can be called
> from IRQ context as well?
>
> You basically need:
>
> - irq-safe get_vm_area
> - irq-safe pmd_alloc_kernel
> - irq-safe pte_alloc_kernel
>
> Last time I looked, all the above were not irq-safe.
No, I realise they're not safe at the moment - I'm working on that
too.
-- David Gibson | For every complex problem there is a david@gibson.dropbear.id.au | solution which is simple, neat and | wrong. http://www.ozlabs.org/people/dgibson - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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