On Sun, 8 Sep 2002, Linus Torvalds wrote:
> As far as I can tell, the only time when this might be an advantage is
> an SMP machine with multiple devices sharing an extremely busy irq line.
> Then the per-isr in-progress bit allows multiple CPU's to actively
> handle several of the devices at the same time.
>
> Or is there some other case where this is helpful?
it could also improve latency of a faster interrupt source that shares its
irq line with a slow (but still frequent) handler. (such as SCSI or ne2k.)
This is both on UP and on SMP.
although this might be less of an issue these days.
Ingo
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This archive was generated by hypermail 2b29 : Sun Sep 15 2002 - 22:00:16 EST