Linus,
The raid5 xor checksums use MMX/SSE state and are not preempt-safe.
Attached patch disables preemption in FPU_SAVE and XMMS_SAVE and
restores it in FPU_RESTORE and XMMS_RESTORE - preventing preemption
while in fp mode.
Please, apply.
Robert Love
diff -urN linux-2.5.31/include/asm-i386/xor.h linux/include/asm-i386/xor.h
--- linux-2.5.31/include/asm-i386/xor.h Sat Aug 10 21:41:20 2002
+++ linux/include/asm-i386/xor.h Sat Aug 24 20:14:43 2002
@@ -20,6 +20,7 @@
#define FPU_SAVE \
do { \
+ preempt_disable(); \
if (!test_thread_flag(TIF_USEDFPU)) \
__asm__ __volatile__ (" clts;\n"); \
__asm__ __volatile__ ("fsave %0; fwait": "=m"(fpu_save[0])); \
@@ -30,6 +31,7 @@
__asm__ __volatile__ ("frstor %0": : "m"(fpu_save[0])); \
if (!test_thread_flag(TIF_USEDFPU)) \
stts(); \
+ preempt_enable(); \
} while (0)
#define LD(x,y) " movq 8*("#x")(%1), %%mm"#y" ;\n"
@@ -543,6 +545,7 @@
*/
#define XMMS_SAVE \
+ preempt_disable(); \
__asm__ __volatile__ ( \
"movl %%cr0,%0 ;\n\t" \
"clts ;\n\t" \
@@ -564,7 +567,8 @@
"movl %0,%%cr0 ;\n\t" \
: \
: "r" (cr0), "r" (xmm_save) \
- : "memory")
+ : "memory") \
+ preempt_enable();
#define ALIGN16 __attribute__((aligned(16)))
diff -urN linux-2.5.31/include/asm-x86_64/xor.h linux/include/asm-x86_64/xor.h
--- linux-2.5.31/include/asm-x86_64/xor.h Sat Aug 10 21:41:23 2002
+++ linux/include/asm-x86_64/xor.h Sat Aug 24 20:05:41 2002
@@ -38,7 +38,8 @@
/* Doesn't use gcc to save the XMM registers, because there is no easy way to
tell it to do a clts before the register saving. */
#define XMMS_SAVE \
- asm volatile ( \
+ preempt_disable(); \
+ asm volatile ( \
"movq %%cr0,%0 ;\n\t" \
"clts ;\n\t" \
"movups %%xmm0,(%1) ;\n\t" \
@@ -59,7 +60,8 @@
"movq %0,%%cr0 ;\n\t" \
: \
: "r" (cr0), "r" (xmm_save) \
- : "memory")
+ : "memory") \
+ preempt_enable();
#define OFFS(x) "16*("#x")"
#define PF_OFFS(x) "256+16*("#x")"
-
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This archive was generated by hypermail 2b29 : Sat Aug 31 2002 - 22:00:18 EST