Re: New version of pageattr caching conflict fix for 2.4

From: Benjamin LaHaise (
Date: Fri Jun 14 2002 - 10:28:49 EST

On Fri, Jun 14, 2002 at 06:27:54AM +0200, Andi Kleen wrote:
> Both AMD x86-64 and Intel IA32 documentation states that INVLPG flushes global
> TLBs. The first version of change_page_attr did in fact use __flush_tlb_all,
> but I changed it after checking the docs.

As Andrea pointed out, there is an errata whereby 4MB pages aren't flushed
on the Athlon. If you mask off the low bits of the address for flushing,
that should fix the problem, and sounds like a plausible explanation for
the failure I saw.


ps. s/La Haise/LaHaise would be nice, too.

"You will be reincarnated as a toad; and you will be much happier."
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