Re: PCI DMA to small buffers on cache-incoherent arch

From: David S. Miller (
Date: Tue Jun 11 2002 - 22:25:53 EST

   From: David Brownell <>
   Date: Tue, 11 Jun 2002 08:12:35 -0700
   Should the dma mapping APIs try to detect the "DMA buffer starts in
   middle of non-coherent cacheline" case, and fail? That might be
   worth checking, catching some of these errors, even if it ignores
   the corresponding "ends in middle of non-coherent cacheline" case.
   And it'd handle that "it's a runtime issue on some HW" concern.
This brings back another issue, returning failure from pci_map_*()
and friends which currently cannot happen.

   Or then there's David Woodhouse's option (disable caching on those
   pages while the DMA mapping is active) which seems good, except for
   the fact that this issue is most common for buffers that are a lot
   smaller than one page ... so lots of otherwise cacheable data would
   suddenly get very slow. :)
Remember please that specifically the DMA mapping APIs encourage use
of consistent memory for small data objects. It is specifically
because non-consistent DMA accesses to small bits are going to be very
slow (ie. the PCI controller is going to prefetch further cache lines
for no reason, for example). The non-consistent end of the APIs is
meant for long contiguous buffers, not small chunks.

This is one of the reasons I want to fix this by making people use
either consistent memory or PCI pools (which is consistent memory
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This archive was generated by hypermail 2b29 : Sat Jun 15 2002 - 22:00:24 EST