Re: PCI DMA to small buffers on cache-incoherent arch

From: David S. Miller (
Date: Sat Jun 08 2002 - 19:53:25 EST

   From: Roland Dreier <>
   Date: 08 Jun 2002 17:40:24 -0700
   Or should we leave that usage unless it is observed causing
   problems (since we almost always get lucky and don't touch the rest
   of the cache line near the DMA)?
I think passing in a 4 byte chunk and assuming the rest of the
cacheline is unmodified is a valid expectation the more I think
about it.

This means what MIPS is doing is wrong. For partial cacheline bits it
can't do the invalidate thing.
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to
More majordomo info at
Please read the FAQ at

This archive was generated by hypermail 2b29 : Sat Jun 15 2002 - 22:00:13 EST