On Tue, 23 Apr 2002, Saxena, Sunil wrote:
> The correct sequence for initializing MMX/SSE/SSE2 CPU state (I exchanged
> mail with Linus) is:
>
> memset(&fxsave, 0, sizeof(struct i387_fxsave_struct));
> fxsave.cwd = 0x37f;
> fxsave.mxcsr = 0x1f80;
>
> fxrstor(&fxsave);
>
> The above is architectural feature and you can expect this to work in the
> future. Intel will work to document this in our Monthly Specification
> Updates and update "IA-32 Intel(R) Architecture Software Developer Manual"s.
Sure is nice to see some vendor support!
-- bill davidsen <davidsen@tmr.com> CTO, TMR Associates, Inc Doing interesting things with little computers since 1979.- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Tue Apr 30 2002 - 22:00:10 EST