On Sat, 20 Apr 2002, Andrea Arcangeli wrote:
>
> I mean, if they change the registers layout, and so if they require a
> different empty FPU state, they must as well add yet another bitflag to
> enable SSE3, if they don't the chip isn't backwards compatible.
I have unofficial confirmation from Intel that the way to architecturally
initialize the FPU state is indeed something like
memset(&fxsave, 0, sizeof(struct i387_fxsave_struct));
fxsave.cwd = 0x37f;
fxsave.mxcsr = 0x1f80;
fxrstor(&fxsave);
and the person in question is trying to make sure this is documented so
that we won't be bitten by this in the future.
Linus
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This archive was generated by hypermail 2b29 : Tue Apr 23 2002 - 22:00:36 EST