Paul Mackerras wrote:
> > Little-endian dword:
> >
> > 3 2 1 0
> > 80 86 71 11
>
> So we have byte[0] = 0x11, byte[1] = 0x71, byte[2] = 86, byte[3] =
> 0x80, right? If we read individual bytes we will get the same results
> on a little-endian or a big-endian platform.
>
> On a little endian platform, pci_read_config_dword will return
> 0x80867111, since byte 0 is the least-significant byte. Thus we have
> vendor id = 0x7111 and device-id = 0x8086.
>
> On a big-endian platform a 32-bit read will return 0x11718680 (since
> byte 0 is the most significant byte), and pci_read_config_dword will
> byte-swap that to 0x80867111. Thus we once again have vendor id =
> 0x7111 and device-id = 0x8086.
>
Actually, in our case, the first dword was 0x80867111 (little-endian),
so when we read the first dword, we got 0x80867111 (big-endian),
since we were reading a dword, not individual bytes. If we read the
individual bytes, we do get the right bytes, but the PCI subsystem
returns the same bytes to us for either a little-endian or big-endian
dword read, since it doesn't know if the processor is big-endian
or little-endian (The PowerPC can be both, or different processors
on the same bus can be different at the same time).
> Doesn't the fact that people have been successfully using PCI devices
> in PowerPC machines since 1995 or 1996 suggest to you that it might be
> your understanding that is faulty rather than the code? :)
Well, when you have new hardware, a new compiler (with known bugs),
and a new processor chip, the fact that it works for others doesn't mean
that it's right. It hardly seems wise to assume there are no problems
left
in the software. My original question was "How can this work (since it
clearly must be working) when it does not appear to be correct?"
It's not as if the code is clearly documented that it depends upon the
PCI hardware knowing if it should return big-endian or little-endian
data.
jim
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This archive was generated by hypermail 2b29 : Tue Apr 23 2002 - 22:00:36 EST