> > Intel folks are actually saying even back in Pentium MMX days that it isnt
> > guaranteed that the FP/MMX state are not seperate registers
>
> In this case it would be possible to only do the explicit clear
> when the CPU does support sse1. For mmx only it shouldn't be needed.
> For sse2 also not.
Do you have a documentation cite for that claim ?
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This archive was generated by hypermail 2b29 : Tue Apr 23 2002 - 22:00:20 EST