On Tue, Jan 08, 2002 at 01:12:04PM +0100, Maciej W. Rozycki wrote:
A possible reason is the 8259A in the chipset deasserts its INT
output late enough for the Athlon CPU's local APIC to register
another ExtINTA interrupt sometimes, possibly under specific
circumstances.
Actully... we could potentially measure this... after an interrupt it
serviced (or before, or both) we could store the interrupt source
globally and the cycle counter... when a suprrious interrupt is
received check the last interrupt and how long ago it was and then
start looking for a pattern...
--cw
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