I'm trying to help track down some infrequent and difficult to reproduce pci bus
parity errors that we're seeing on a cPCI card, and one of the things that has
been suggested is that it may have something to do with DMA coherency between
devices and the processor.
Can someone point me to the proper code/information that deals with how the
processor knows that the memory corresponding to the ethernet device is no
longer up-to-date? Is it somehow marked as non-cacheable, or is it snooped,
explicitly flushed, or what?
The platform in question is a Motorola MCPN765 card, with a PPC7400 processor,
running a modified 2.2.17 kernel.
Thanks,
Chris
-- Chris Friesen | MailStop: 043/33/F10 Nortel Networks | work: (613) 765-0557 3500 Carling Avenue | fax: (613) 765-2986 Nepean, ON K2H 8E9 Canada | email: cfriesen@nortelnetworks.com - To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
This archive was generated by hypermail 2b29 : Thu Nov 15 2001 - 21:00:23 EST