Re: SMP processor rework help needed

From: Manfred Spraul (
Date: Mon Oct 15 2001 - 12:16:16 EST

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> For intel the initial determination is made having the cpus race on
> the apic bus. The cpu that sends a message first gets the lowest
> apicid. Though I need to see how the P4 Xeon does it, as the apic
> bus is actually unused.


24547202.pdf: (i.e. volume 3 of the ia32 SDM)
The APIC ID register is loaded at power up by sampling configuration
data that is driven onto pins of the processor. For the Pentium 4 and P6
family processors, pins A11# and A12# and pins BR0# through BR3# are
sampled; for the Pentium processor, pins BE0# through BE3# are sampled.

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