Linux Sparc V9 code optimazation

Date: Fri Jun 29 2001 - 12:20:29 EST

To any Sparc guru,

This question relates to the effect of instruction alignment on a Sparc's
Prefetch/Dispatch unit.

Just how exactly does the branch prediction bits for instruction pairs in
the I-Cache utilized.

I'm trying to figure out the consequences of an odd word fetch into an
Instruction cache line with a the fourth
instruction being another branch.

Please cc me as I am currently not on the mailing list.

Ramil J.Santamaria
Toshiba America Information Systems
(949) 461-4379
(949) 206-3439 - fax

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This archive was generated by hypermail 2b29 : Sat Jun 30 2001 - 21:00:22 EST